COMMENT ⊗   VALID 00004 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002	This file contains corrections, additions and updates to the UUO Manual,
C00014 00003	25. THE NEW AD & DA CONVERTERS
C00031 00004	26. The CORE2 UUO will take the direct (error) return if you ask it
C00032 ENDMK
C⊗;
This file contains corrections, additions and updates to the UUO Manual,
including new UUOs that have been added since the manual went to press.

1.  The only UUO spacewar processes on the PDP-6 can issue is the
    DISMIS UUO.  (I think any UUO given on the 6 has the effect of DISMIS.)

2.  On p. 126, the 2nd line of 1st paragraph should read "even" instead
    of "ever".

3.  In disk file protection key, read protection (2 bit) implies
    protection protection (4 bit) for any group of users.

4.  INTJEN UUO turns on bits in the interrupt mask, not in the interrupt
    enablings.

5.  Non-ARPA PTYs never run LOGOUT when logging out. ARPA PTYs do run LOGOUT.

6.  RENAME can be done after ENTER without doing a CLOSE first unless
    the file being renamed is replacing an existing file (another file
    had same name when ENTER was done).  In that case a CLOSE must be
    done first (which will delete the original file).

7.  IOPUSH CHN,ID	;[OP=724]
    <pdlov>
    <channel pushed>

	Pushes io channel CHN on io pdl. Channel CHN may now be used
	without affecting the device you pushed. The ID is saved with
	the channel for use with IOPOP and IOPDL.

8.  IOPOP CHN,ID	;[OP=725]
    <stack empty>
    <success>

	Finds first channel on stack with ID searching down from top. If
	ID = 0 then uses top of stack. If not found, takes error return.
	Releases channel CHN, places the device from the stack into that
	channel, and compresses that entry out of the stack.

9.  IOPDL N,ID		;[OP=726]

	IOPDL 0,

		Does IOPOP for each device on the io pdl. The channel it
		uses is the same one the device was pushed from.

	IOPDL 1,

		Releases all devices from stack without affecting devices
		not currently pushed on stack.

	IOPDL 2,ID
	<error return>
	<device released>

		Finds device with ID same as for IOPOP, then releases it
		without affecting any other devices. The stack is compressed.

10. MOVE AC,[CODE,,JOB #]
    GETPRV AC,			;[OP=047, ADR=400115] CALLI 400115
    <always return here>

	If job # illegal, uses current job.

	CODE = 0
		Get active privileges for job #.  Return them in AC.
	CODE = 1
		Get passive privileges for job #.  Return them in AC.

11. TTYSKP CHN,			;[OP=047, ADR=400116] CALLI 400116

	If no device on channel CHN, "IO TO UNASSIGNED CHANNEL" error.
	If not TTY, never skip.
	If TTY, will skip if next input will not hang.

12. MOVEI AC,ADDR
    DIAL AC,			;[OP=047, ADR=400117] CALLI 400117
    <error return, error code in AC>
    <success return>

    ADDR:   DIALER #,,FUNCTION CODE
	    <any further args as needed>

    Error codes:

      0  Illegal dialer #.
      1  Dialer in use by someone else.
      2  Don't meet ownership requirements (currently, don't have TTY11 inited)
      3  Attempt to dial while call in progress (should hang up first)
      4  Dialing failure.

    Function codes:

	0	Claim dialer. Must be done before any other function can be
		performed with this dialer #.

	1	Get dialer status. Returns:

			<last interrupt coni>,,<current coni>

		in AC.

	2	Dial a number. ADDR+1 is area code in the following format:

		Bit	 0	     17 18 21 22 25 26 29 30    35
			__________________________________________
			|	       |     |     |     |       |
		Digit	|	       |  1  |  2  |  3  |       |
			|______________|_____|_____|_____|_______|

		ADDR+2 is the rest of the number in this format:

		Bit	 0   5 6 7 8  11 12 15 16 19 20 23 24 27 28 31 32 35
			_____________________________________________________
			|     | | |     |     |     |     |     |     |     |
		Digit	|     |A|V|  1  |  2  |  3  |  4  |  5  |  6  |  7  |
			|_____|_|_|_____|_____|_____|_____|_____|_____|_____|

		A on, dial area code.

		V on, call is "VOICE" call. Will switch to AD/DA when call
			completed. Not implemented yet!

	3	Hang up.

	4	Release dialer (automatically done if you release TTY11).

13. LOOKUP followed by ENTER now updates date/time in UFD entry for file.

14. RUNMSK is now a no-op (may become illegal soon).

15. WHO AC,		;[OP=047, ADR=400112] CALLI 400112

	AC right should contain address of 22-word block for returned asciz string.
	If AC left contains legal job #, return who line for that job as asciz text.
	If AC left = 0 or > legal job #, return who line for current job.
	If AC left < 0, return system who line.
	If no job for legal job #, returns null string.

16. TTYJOB AC,		;[OP=047, ADR=400113] CALLI 400113

	If AC is 0 to max TTY line number, returns in AC the job # of owner.
	Sign bit will be on if this is not owners "console".
	If AC is -<PTY line #>, returns in AC the job # of job controlling PTY.
	All other args return 0 in AC.

17. PTYs are initialized with bits 6 (PTYLIN), 10 (PTYUSE), 13 (FCS)
    and 16 (XON) (4222,,0 bits) on in the line characteristics.  The UUO
    manual (p. 48) does not mention the FCS bit being on for a new PTY.

18. In the UUO manual on the first line of p. 148 (section 13.3), it
    should say "(bit 28)" instead of "(bit 31)" (bit to set to get error
    return instead of error message when LPT is hung).

19. IMP MTAPE 13 (Bless Host) is now a no-op since there is no longer
    a system table of dead hosts.  All hosts are assumed alive except for
    an instant after the IMP network has returned a Host Dead message in
    response to an attempt by us to send that host a message.

20. PPACT apparently erases all deactivated pieces of paper even on
    Data Discs.  And PPSEL calls PPACT with only the selected piece of
    paper activated.

21. When doing 8-bit byte buffered IMP output, any of the four bytes
    in the last used word in any buffer can be suppressed from being
    transmitted to the IMP by setting the corresponding bit of the low
    order four bits of the same word.  For example, if the word pointed
    to by the byte pointer in your output buffer header contains
    776655,,443307, then only the first (high-order) byte of this word
    will be transmitted.
    That is, bit 32 (0,,10 bit) suppresses the first byte  (776000,,0 byte),
             bit 33  (0,,4 bit) suppresses the second byte (001774,,0 byte),
             bit 34  (0,,2 bit) suppresses the third byte  (3,,770000 byte),
    and      bit 35  (0,,1 bit) suppresses the fourth byte (0,,007760 byte).

22. The DEVNUM UUO is listed four times in the manual as CALLI 4000104 whereas
    it should really be CALLI 400104 (deleting extra zero).

23. The left half of each entry in the JOBJDA block of the job data
    area contains the channel-status bits, as returned (in the right half
    of an AC) by the CHNSTS UUO.  However, these bits and the device data
    block (DDB) address in the right half are not kept up to date by the
    system.  These cells are guaranteed correct only when your job is not
    running; they will in general also be correct if you have not done
    any I/O since the beginning of the current quantum of run time.

24. The left half of a TTY's entry in TTYTAB (see monitor pointers)
    contains the number of the next TTY in the given TTY's talk ring, if
    that TTY is in a talk ring; when a TTY is not in a talk ring, the
    left half of its TTYTAB entry contains the TTY's own line number.
25. THE NEW AD & DA CONVERTERS

The new analog-to-digital converter (ADC) and digital-to-analog
converter (DAC) are devices on the PDP-6's IO bus which may be
operated in dump mode (17) only. They provide input and output of
digitized waveforms conventionally representing speech, music, or
other acoustical signals.

Both the DAC and the ADC can operate in a manner such that the data
transfer UUO (INPUT, or IN, for ADC, OUTPUT, or OUT, for DAC) does
not wait for the transfer to finish before returning to the user.
This feature is enabled by the 100 bit (called CONT) in the IO status
word. In this case, the user must have three separate buffers. There
is the buffer that the device is operating on, the one that is
waiting, and the one the user is operating on. If you use just two
buffers, you may find that you are operating on the same buffer the
system is operating on. As you give data transfer UUOs, the first one
will start the transfer and return immediately. The second one will
store the IOWD and return immediately. It is not until the third one
is given that the UUO will wait. It will wait for the buffer
specified by the first UUO to become free, and start the second
buffer, before it will accept the address of the third buffer and
return.

If either the ADC or the DAC loses a sample, the LOST bit (bit 2000)
is set in the IO status word. This means a discontinuity has occured
in the signal.

The ADC can be data-triggered. By setting the CYCLE bit (bit 200) in
the IO status word, the ADC does not move beyond the first buffer,
but instead transfers continuously into the first buffer. When it
gets to the end of the first buffer, it goes back to the beginning
automatically. This process continues until a sample comes in that is
larger than some threshold (user settable). When such a sample
occurs, the system goes on to the second buffer and returns to the
user the position in the first buffer that the triggering sample
occurred. For effeciency, the compare is not made with each sample in
the word, but instead with just the high-order sample. You must be in
CONT mode to guarantee continuity between the first and second
buffers.

When the ADC in CYCLE mode goes to the second buffer, the CYCDON bit
(20 bit) is set in the IO status word. You can cause the ADC to start
cycling again by clearing this bit. This is only useful if you know
which buffer it is in. It will go into CYCLE mode on the next buffer.

The ADC and the DAC can be made to start simultaneously. This is done
by turning on the IOSYNC bit (40 bit) in the IO status words of both
devices (they are different devices, require different INITs). What
happens is that the first data transfer UUO (of either device) does
not actually start the transfer. When the first data transfer UUO for
the other device is given, then both devices will begin. Note that
either UUO (ADC or DAC) can be given first. The second UUO will start
the transfer. You must be in CONT mode for the device whose UUO is
given first, or you will not return from the UUO. The system will
only wait one minute between the two UUOs.

If you are in CYCLE mode on the ADC, and in IOSYNC mode on both
devices, you can specify that the DAC is to be started after the ADC
is advanced to the second buffer and not just at the beginning of
input. This is done by setting the IOAFT bit (bit 4000) in the ADC IO
status word. This will prevent the DAC's being started until the ADC
advances to the second buffer.

The device-specific bits of the IO status word are shown below. The
asterik represents bits that are only meaningful to the ADC.

    Bits     Octal      Mnemonic       Meaning

   *24	     4000       IOAFT	       Begin DAC only after ADC has
				       moved on to second buffer, i.e.
				       IOSYNC∧IOAFT∧CYCDON ⊃ Start DAC

    25       2000       LOST           Data missed

   *28       200        CYCLE	       Causes ADC to transfer repeatedly
				       into the first buffer until
				       some input sample exceeds a
				       preset threshold.

    29       100        CONT	       Causes system to return to the
				       user immediately from a data
				       transfer UUO.

    30       40         IOSYNC         ADC and DAC will be started
				       simultaneously.

   *31       20         CYCDON         Indicates ADC has moved from
				       first input buffer to the
				       second. Only relevant in
				       CYCLE mode.

To set parameters like sampling rate, channel multiplexing, and such,
the MTAPE UUO has been drafted to serve this special function. An
MTAPE to either the ADC or the DAC has as its effective address the
address of a 3-word (2-word for DAC) block which is formatted as
follows:


	<*CYCLE threshold>,,<Speed*1000+Packing*100+Nchans>
	<address for `RUN' flag>
	<*Input select>,,<*address for CYCLE pointer>

Speed is coded as follows:

    Code     Clock rate (per channel!!!)
     0	       6.4KHz
     1	       12.8KHz
     2	       25.6KHz
     3	       51.2KHz (Highest ADC rate)
     4	       102.4KHz
     5	       204.8KHz

Packing is coded as follows:

    Code     Packing mode
     0        12-bit two's complement bytes packed 3 to a word
     1	      18-bit two's complement bytes packed 2 to a word
     2        9-bit incremental floating-point bytes packed 4 to a word
		(DAC only)

Note that the 18-bit byte has only 16 significant bits for the DAC
and only 14 significant bits for the ADC. In the DAC, the low order 2
bits of each byte are ignored. In the ADC, the low order 4 bits of
each byte are set to zero.

These packing modes are diagrammed below:

12-bit mode (code 0):
____________________________________________________________
|0                11|12              23|24               35|
|   SAMPLE 1        |     SAMPLE 2     |     SAMPLE 3      |
|___________________|__________________|___________________|

18-bit mode (code 1):
____________________________________________________________
|0                        17|18                          35|
|           SAMPLE 1        |          SAMPLE 2            |
|___________________________|______________________________|

9-bit mode (code 2, DAC only):
____________________________________________________________
|0   3|4     8|9  12|13    17|18 21|22   26|27 30|31     35|
| EX1 | MANT1 | EX2 | MANT2  | EX3 | MANT3 | EX4 |  MANT4  |
|_____|_______|_____|________|_____|_______|_____|_________|

This last mode is called Incremental floating point (abbreviated IFP
mode). Each 9-bit byte is decoded into a 4 bit exponent and a 5-bit
mantissa. The mantissa is shifted left the number of places
represented by the number in the exponent and is added into the
current position of the DAC to produce the new position. The sign bit
is inferred from the mantissa, it is not explicit. The sign bit is
taken to be the complement of the high order mantissa bit, and is
spread throughout the number before the shifting occurs.

To restate, the DAC has, for each channel, a 16 bit register, called
the FLTMEM register. These registers are cleared at the beginning of
a transfer. In IFP mode, a 9-bit byte is unpacked from the input
word. The high order 4 bits of that byte go into a counter, the low
order 5 bits go into the low-order 5 bits of a 21 bit (16+5) shift
register. The complement of the high order bit of the mantissa is
stored in the high-order 16 bits of that 21-bit shift register. This
entire register is shifted left the number of places (0 to 15)
represented by the number currently in the counter (the exponent).
The high order 16 bits of this register are then added into the
FLTMEM register for this channel and the sum is stored back into the
FLTMEM register. This sum is also delivered to the DAC.

Notice that this means that a 9-bit byte with all bits zero does not
represent a change of zero in the FLTMEM register. A zero byte will
infer a sign bit of 1, which will be spread throughout the word and
will result in a word of -1. 20 is the `official' code for zero. This
has the high order bit of the mantissa on and all other bits zero.

Nchans is decoded as follows:
    Code      Meaning
     0         unused. Currently same as 3.
     1         Monaural (1-channel only)
     2         Stereo (2 channels)
     3         Quadraphonic (4 channels)

For multiple channels, successive samples go to successive channels.
For example, in Stereo mode (code 2), the first sample goes to
channel 1, the second sample goes to channel 2, the third sample goes
to channel 1 again, the fourth to channel 2, and so on.

In CYCLE mode for the ADC, the input is directed into the first
buffer until the high order sample in a word exceeds the threshold.
This threshold is specified in the left half of the first word of the
MTAPE block.

The right half of the second word of the MTAPE block is the address
of the `RUN' flag (may be zero to inhibit feature). When the ADC or
the DAC is started, this cell is set to -1. When the ADC or DAC is
stopped, this cell is set to 0. In this manner, one can tell when his
transfer is actually occurring. Since the ADC and the DAC are given
separate MTAPEs, they can have separate RUN flags, as well as
separate clock rates, numbers of channels, and packing modes.

The third word of the MTAPE block is only relevant to the ADC. The
right half specifies the address where the buffer pointer is to
be places in CYCLE mode. What you get is the IOWD at the point
the threshold was exceeded, relocated to a relative address within
your core image. The address part of this word (the right half)
will point to the word containing the sample that exceeded the
threshold.

The left half of the third word of the MTAPE block specifies the
input multiplexing address for the ADC. Not only are there four input
channels that are serviced sequentially, but all four channels can be
switched to an alternate four inputs. This is specified by setting
the sign bit of the third word of the MTAPE block to 1. At some point
in the future, this left half may contain an honest multiplexing
address, such that input can be obtained from any of a number of
sources, but for now, you just have the four main channels and the
four alternate channels.

Neither the ADC nor the DAC take a standard monitor dump mode command
list. The effective address of the UUO points to a single IOWD. It
does not have to be followed by a zero.
26. The CORE2 UUO will take the direct (error) return if you ask it
    to make a new upper segment for you and there are no job slots
    available.

27. PTJOBX command number 7 is CLRBFI.  It has the effect of having
    done a CLRBFI for the TTY specified by the PTJOBX.